1. Field of the Invention
The present invention relates to a digital video tape recorder (digital VTR) which can record and reproduce a digital high-definition video signal and a standard digital video signal with a compatibility.
2. Description of the Prior Art
Professional digital video tape recorders that can record and reproduce a high-definition video signal (hereinafter simply referred to as an HD signal) in the form of a digital signal have already been developed and become commercially available. If the digital video tape recorder has a compatibility with a conventional standard digital video signal (hereinafter simply referred to as an SD signal) when it is modified as a consumer digital video tape recorder, then it can be expected that consumer digital video tape recorders will be popularized smoothly, in particular, at the transition stage. The assignee of the present application has previously proposed a video signal recording system in which a compatibility between the HD signal and the SD signal can be established (see Japanese Laid-Open Patent Publication No. 3-79155).
FIG. 1 of the accompanying drawings shows in block form an arrangement of a recording system of a digital video tape recorder that employs such a previously-proposed video signal recording system.
As shown in FIG. 1, a high-definition video signal (HD signal) is supplied to an input terminal 61. The HD signal applied to the input terminal 61 is supplied to an analog-to-digital (A/D) converter circuit 6, in which it is sampled at a sampling frequency of 40.5 MHz, for example, and also encoded in a predetermined encoding manner to provide a digital signal composed of a full-scanning line luminance signal and line-sequential color difference signals, for example. This digital signal is what might be called a 12:4:0 digital signal.
This digital signal is supplied to a low-pass filter (LPF) 63 which separates the sub band in the vertical direction, for example, and a high-pass filter (HPF) 64. The low-pass filter 63 and the high-pass filter 64 are each formed of a so-called QMF filter. Output signals of the low-pass filter 63 and the high-pass filter 64 are respectively supplied to and decimated to 1/2 by decimation circuits 65, 66, thereby forming a so-called 6:2:0 digital signal having a sampling frequency of 20.25 MHz that is matched with that of the digital signal of the SD signal which will be described later on.
An output signal from the decimation circuit 65 is supplied to a discrete cosine transform (DCT) circuit 67 which is used to compress data. An output signal from the discrete cosine transform circuit 67 is supplied to and quantized by a quantizer (Q.sub.1) circuit 68 so that the bit rate of the recording signal becomes 25 Mbps, for example. A signal from the quantizer circuit 68 is supplied to a variable length coder (VLC) circuit 69 and the signal thus processed by the variable length coder circuit 69 is supplied through a switch 70 to an encoder (ENC) circuit 71. The signal supplied to the encoder circuit 71 is processed in a predetermined recording signal processing fashion such as an error correction or the like and then fed to a recording head 72.
A signal from the decimation circuit 66 is supplied to and quantized by a quantizer (Q.sub.3) circuit 73 so that the bit rate of the recording signal becomes 25 Mbps, for example. A signal from the quantizer circuit 73 is supplied to a run length coder (RLC) circuit 74. A signal from the run length coder circuit 74 is supplied to a variable length coder (VLC) circuit 75. The signal thus processed by the variable length coder circuit 75 is supplied to an encoder (ENC) circuit 76, in which it is processed in a predetermined recording signal processing fashion such as an error correction or the like, and then fed to a recording head 77. Therefore, the HD signal is recorded on a tape (not shown) at the bit rate of 25+25=50 Mbps by the recording heads 72, 77.
A standard video signal (SD signal) is supplied to an input terminal 78. The SD signal applied to the input terminal 78 is supplied to an A/D converter circuit 79, in which it is sampled by a sampling frequency of 20.25 MHz, for example, and encoded in a predetermined encoding fashion to provide a so-called 6:2:0 digital signal composed of a full-scanning line luminance signal and line-sequential color difference signals. In the digital signal of the SD signal, the SD signal has an aspect ratio of 16:9. The present invention is not limited thereto and can be applied to the case such that the SD signal has an aspect ratio of 4:3 (e.g., 4:2:0 digital signal having a sampling frequency of 13.5 MHz).
A signal from the A/D converter circuit 79 is supplied to a discrete cosine transform (DCT) circuit 80 that is used to compress data, for example. A signal from the discrete cosine transform circuit 80 is supplied to and quantized by a quantizer (Q.sub.1 ') circuit 81 such that the bit rate of the recording signal becomes 25 Mbps, for example. A signal from the quantizer circuit 81 is supplied to a variable length coder (VLC) circuit 82 and the signal thus processed by the variable length coder circuit 82 is supplied to the switch 70.
Therefore, a high band signal of the HD signal and a low band signal of the HD signal or the SD signal are respectively recorded on alternate tracks as shown by a track pattern of FIG. 2 of the accompanying drawings. Therefore, the HD signal can be reproduced by reproducing all of these tracks and the SD signal can be reproduced by reproducing the tracks of the SD signal. The low band signal can be reproduced as the SD signal by reproducing the tracks of the low band signal of the HD signal, thereby achieving a compatibility between the HD signal and the SD signal.
According to the above conventional apparatus, the HD signal is separated into vertical sub band signals and then decoded as schematically shown in FIG. 3 of the accompanying drawings, for example.
As shown in FIG. 3, a signal applied to an input terminal 91 is supplied to a high-pass filter (HPF) 92 and a low-pass filter (LPF) 93. Each of the high-pass filter 92 and the low-pass filter 93 is formed of the so-called QMF filter. Output signals from the high-pass filter 92 and the low-pass filter 93 are supplied to decimation circuits 94, 95 and thereby being decimated to 1/2, respectively. The decimated signals from these decimation circuits 94, 95 are supplied to a transmission system 96 through which a recording signal and a reproduced signal are transmitted.
Signals from the transmission system 96 are supplied to interpolation circuits 97, 98, in which the decimated signals are interpolated. Signals from these interpolation circuits 97, 98 are supplied to filters 99, 100. These filters 99, 100 also are formed of the so-called QMF filters and output signals of these filters 99, 100 are added by an adder circuit 101 and then delivered to an output terminal 102.
The QMF is an FIR (finite impulse response) filter that is formed of a series circuit of a plurality of 1H (H is a horizontal period) delay circuits. x.sub.(n) assumes an input signal to the circuit and [ x].sub.(n) assumes an output signal of this circuit (where [ x] represents the overlapping state of the input and output signals). Further, response characteristics of the filters 92, 93, 99 and 100 are defined as:
92: H.sub.1(z) =Z[h.sub.(n) ]
93: H.sub.2(z) =H.sub.1(-z) =Z[-1).sup.n h.sub.(n) ]
99: H.sub.1(z) : h.sub.(n)
100: -H.sub.1(z)=-H.sub.1(-z) =Z[(-1).sup.n+1 h.sub.(n) ]
where Z[ ] represents the Z conversion.
Thus, the response characteristic of the entire circuit is expressed by the following equation (1): ##EQU1## If the following equation (2) is satisfied, EQU H.sub.2 (.omega.)=H.sub.1 (.omega.+.pi.) EQU H(.omega.)=H(z).vertline..sub.z=e.sbsb.j.spsb..omega. ( 2)
then the frequency response characteristic is expressed as: ##EQU2##
Accordingly, using a symmetric FIR filter having taps the number of which is M as an QMF filter yields: ##EQU3## Therefore, the frequency response is expressed as: ##EQU4## Further, if M is even, then the above frequency response is expressed as: ##EQU5## Accordingly, if the following equation (7) is satisfied, EQU .vertline.H.sub.1 (.omega.).vertline..sup.2 +.vertline.H.sub.1 (.omega.+.pi.).vertline..sup.2 =1 (7)
then, in the output signal [ x].sub.(n), after the HD signal of the input signal x.sub.(n) is separated into the sub band signals of the vertical direction and then transmitted, these sub band signals can be synthesized and decoded from a theory standpoint. FIG. 4 of the accompanying drawings shows an example of frequency characteristics of the respective filters and FIG. 5 of the accompanying drawings shows an example of impulse responses of the taps of the QMF filter.
In the above conventional apparatus, the low band signal which results from separating the HD signal into the sub band signals of the vertical direction is quantized in accordance with the bit rate of the SD signal by the quantizer circuit 68 and a large amount of data are reduced, thereby causing a distortion to occur due to the quantization. As a consequence, if the low band signal and the high band signal having distortions are synthesized to restore the HD signal upon playback, the quality of the reproduced image will be deteriorated.
When the above-mentioned discrete cosine transform (DCT) is carried out as a data compressing method in order to record the HD signal, the energy is concentrated in particular, in the low band. Therefore, if the low band signal is quantized at the quantization amount corresponding to the bit rate of the SD signal, then a large distortion occurs in the low band signal. Consequently, when the low band signal and the high band signal are synthesized to provide the HD signal, the distortion is increased more, thereby the quality of the reproduced image being deteriorated remarkably.